Virtualization Technology For AMD Architecture Steve McDowell

Virtualization Technology For AMD Architecture Steve McDowell Division Marketing Manager Computation Products Group AMD steven.mcdowell @ amd.com Geoffrey Strongin Platform Security Architect Computation Products Group AMD geoffrey.strongin @ amd.com

Session Outline Driving Towards Virtualization Solving the IT Department’s Utilization Dilemma Virtual Machine Approaches System Architecture Matters x86 Needs Help “Pacifica” Architecture Core Architecture Access Control Interrupts Secure System Management Mode Device Protection

Session Goals Attendees should leave this session with the following A better understanding of virtualization use cases Understanding of hardware assist for virtualization and AMD’s virtualization technology, codenamed “Pacifica” Knowledge of where to find resources for learning more about AMD and virtualization

Virtualization Virtualization is the pooling and abstraction of resources in a way that masks the physical nature and boundaries of those resources from the resource users

Problems With “Physical Boundaries” Today, IT Departments often have lots of pools of excess capacity and no way to share them Most applications are small 93% of x86 servers are 1 or 2-way Small applications don’t consume servers Applications typically have dynamic workloads Currently, x86 servers run at 10-20% utilization Mainframes typically run at 75-85% utilization The costs add up for running lots of under-utilized servers

Virtualization In Servers Benefits over non-virtualized environments Reduced Hardware Cost Higher physical resource utilization Smaller footprint (power, space, cooling, etc.) Improved flexibility and responsiveness Resources can be adjusted dynamically Enables On-Demand and Adaptive Enterprise operating environments

Virtualization In Clients Used for legacy support for enterprises who need to support applications on older Operating Systems (OS) side-by-side with new technology Test and Development Isolate development environments from production work Emerging use cases for management partitions, which may reduce IT support costs Heart of next generation security – allow trusted and untrusted partitions to co-exist Have partitions with different levels of security; The environment is designed to allow security policies to be reinforced

Virtual Machine Approaches Carve a Server into Many Virtual Machines Hosted Virtualization Hypervisor-based Virtualization App App App App Guest OS Guest OS Guest OS Guest OS Virtualization Software Host Operating System X86 Hardware Virtualization software manages resources between Host and Guest Operating Systems Application can suffer decreased performance due to added overhead Mgmt Partition Hypervisor AMD64 w/“Pacifica” Virtualization Software (Hypervisor) is the host environment Designed to enable better software performance by eliminating some of the associated overhead If hardware is available, the Hypervisor can be designed to take advantage of it

System Architecture Makes A Difference Legacy Architectures based around front-side bus aren’t scalable for today’s virtualization needs AMD’s Direct Connect Architecture reduces the bottlenecks, enabling efficient partitioning Examples: Today’s Server Architectures

Efficiencies Needed On x86 For Virtualization Virtualization on the existing x86 architecture requires “unnatural acts” to achieve objectives This level of emulation and code rewriting is not required on other architectures Existing approaches add performance overhead and undue complexity, and leave security holes at the most physical levels AMD’s Pacifica technology is designed to take the complexity out of the hypervisor, putting it into the CPU for higher performance, higher security, and lower complexity (compared to traditional software- based approaches) Pacifica brings the x86 into the 21st century On to the Pacifica architecture

Core “Pacifica” Architecture

Core “Pacifica” Architecture Virtual Machine Run (VMRUN) instruction Virtualization based on VMRUN instruction VMRUN executed by host causes the guest to run Guest runs until it exits back to the host World-switch: host guest host Host resumes at the instruction following VMRUN Host instruction Stream VMRUN [rAX] VMCB Data Structure Guest instruction Stream

Core “Pacifica” Architecture Intercepts Guest runs until It performs an action that causes an exit to the host It explicitly executes the VMMCALL instruction The VMCB for a guest has settings that determine what actions cause the guest to exit to host These intercepts can vary from guest to guest Two kinds of intercepts Exception and Interrupt Intercepts Instruction Intercepts Rich set of intercepts allow the host to customize each guest’s privileges Information about the intercepted event is put into the VMCB on exit

Core “Pacifica” Architecture Virtual Machine Control Block All CPU state for a guest is located in the Virtual Memory Control Block (VMCB) data-structure VMRUN: Entry Host state is saved to memory Guest state loaded from VMCB Guest runs VMRUN: Exit Guest state is saved back to VMCB Host state loaded from memory Host state saved using Model Specific Register (MSR): vm hsave pa

Core “Pacifica” Architecture Address translation: Page Tables Input Linear/Virtual Address (LA,VA) CR3 (Physical Address) Page Tables or Directories Guest or Host Physical Address of next table Final Host or Guest Physical Address If this is a “Guest Physical” it must be translated to “Host Physical” via the host page tables when nested paging is enabled

Core “Pacifica” Architecture Address translation: Modes with virtualization

Core “Pacifica” Architecture Shadow Page Tables Memory Protection – Central Processing Unit (CPU) accesses Shadow Page Tables (SPT) Nested Page Tables SPT Constraints on host design Host intercepts guest CR3 Reads/Writes Host monitors guest edits to guest page tables Guest page tables are marked “read only” Host constructs and manages SPT in software Software strategies for this are mature Guest never sees the “real” page tables or the real content of Control Register 3 (CR3) Address Space ID’s (ASID) implemented to improve Translation Look-aside Buffer (TLB) performance VMRUN sets guest ASID

Core “Pacifica” Architecture CPU Access protection SPT sets guest access rights to physical address space No guest access is possible unless a mapping is present in the SPT Covers DRAM and Memory Mapped Input/Output (MMIO) Minimum granularity 4k-bytes VMCB contains a pointer to an IO Permission Map (IOPM) that controls guest access rights to IO Ports Granularity is to 1-byte port VMCB contains a pointer to a Model Specific Register (MSR) permission map that control guest access to MSRs

Core “Pacifica” Architecture Interrupts Processor response to hardware interrupts is setup in the VMCB Two Options Hardware interrupts while guest is running are intercepted causing exit to host Host manages physical APIC Host determines interrupt routing and distribution Host injects virtual interrupts into guests as needed Hardware support for virtual interrupts: v irq, v vector, v prio , v tpr, PHYS IF Interrupts serviced directly in the guest Guest manages physical APIC Host can still inject virtual interrupts Global Interrupt Flag (GIF) Protects host code critical-regions

Core “Pacifica” Architecture System Management mode “Pacifica” implements a flexible architecture for System Management Interrupt (SMI)/SMM Full legacy support for SMI from within host or guest SMI Intercepts Allow host to scrub state if needed followed by native SMI from host Support for “containerized” SMM SMM Mode control via SMM CTL MSR Allow host to scrub state and dispatch the SMM handler from a VMCB

Core “Pacifica” Architecture Containerized SMM flow Host Top: VMMRUN [rAX] (Examine Exit Code) If external SMM (Setup SMM save state) VMRUN [rAX] Loop Top Guest Inst 1 SMI Inst 2 SMI Intercept SMM Code SMM Entry Point RSM RSM Intercept SMM Save State

Core “Pacifica” Architecture Paged Real mode (New) SMM code is designed to start in real mode Memory protections rely on paging, guests must run with paging-enabled Pacifica Solution: Paged Real Mode Only available for guests cr0.pg 1, cr0.pe 0 Host must intercept page faults Real-mode address translation (segment offset) Linear address translation via SPT physical address Correct composition of SPT’s is host responsibility Guest is assuming linear, 0-based mapping

Core “Pacifica” Architecture DMA protection Protection Domains Mapping from bus/device ID to protection domain Device Exclusion Vector (DEV) One DEV per protection domain Permission-checks all upstream accesses 1-bit per physical 4K page (0.003% tax; 128K/4G) of the system address space Protection for both DRAM and Memory Mapped IO space Contiguous table in physical memory

Summary Virtualization is being used in several server scenarios today AMD expects that virtualization will prove valuable for PC clients too There are ways to modify the x86 architecture, so that virtualization is easier to accomplish, performs better, and provides more security AMD’s “Pacifica” technology is being developed for future AMD64 CPUs for servers and clients Key technologies include adding new instructions, supporting different methods of handling page tables, handle host, and guest interrupts (including SMI/SMM), and provide DMA protection

Call To Action Read the “Pacifica” specification to understand hardware assisted virtualization, available at www.amd.com Continue to ensure that your device and driver works with AMD64 on ALL 64-bit enabled Windows Operating Systems Pacifica Technology is for AMD64 CPUs Sign up for AMD’s development center at http:// devcenter.amd.com

Additional Resources Web Resources Main Page: http://www.amd.com Developer Center: http://devcenter.amd.com Related Sessions TWSE05008 Microsoft Virtual Server-Overview and Roadmap TWAR05013 Windows Virtualization Architecture

Community Resources Windows Hardware and Driver Central (WHDC) www.microsoft.com/whdc/default.mspx Technical Communities www.microsoft.com/communities/products/default.mspx Non-Microsoft Community Sites www.microsoft.com/communities/related/default.mspx Microsoft Public Newsgroups www.microsoft.com/communities/newsgroups Technical Chats and Webcasts www.microsoft.com/communities/chats/default.mspx www.microsoft.com/webcasts Microsoft Blogs www.microsoft.com/communities/blogs