Introduction to CMOS VLSI Design Circuits & Layout

Introduction to CMOS VLSI Design Circuits & Layout

Outline CMOS Gate Design Pass Transistors CMOS Latches & Flip-Flops Standard Cell Layouts Stick Diagrams Circuits and Layout CMOS VLSI Design Slide 2

CMOS Gate Design Activity: – Sketch a 4-input CMOS NAND gate Circuits and Layout CMOS VLSI Design Slide 3

CMOS Gate Design Activity: – Sketch a 4-input CMOS NOR gate A B C D Y Circuits and Layout CMOS VLSI Design Slide 4

Complementary CMOS Complementary CMOS logic gates – nMOS pull-down network – pMOS pull-up network inputs – a.k.a. static CMOS Pull-up OFF Pull-up ON Pull-down OFF Z (float) 1 Pull-down ON X (crowbar) Circuits and Layout 0 CMOS VLSI Design pMOS pull-up network output nMOS pull-down network Slide 5

Series and Parallel nMOS: 1 ON pMOS: 0 ON Series: both must be ON Parallel: either can be ON a a 0 g1 g2 (a) (b) a g1 g2 (c) a g1 g2 b Circuits and Layout CMOS VLSI Design 0 1 b b OFF OFF OFF ON a a a a 0 1 1 1 0 1 b b b b ON OFF OFF OFF a a a a 0 0 b 1 b 0 b 1 1 0 g2 a b a g1 a 0 0 b (d) a 0 1 1 0 1 1 b b b b OFF ON ON ON a a a a 0 0 0 1 1 0 1 1 b b b b ON ON ON OFF Slide 6

Conduction Complement Complementary CMOS gates always produce 0 or 1 Ex: NAND gate – Series nMOS: Y 0 when both inputs are 1 – Thus Y 1 when either input is 0 Y – Requires parallel pMOS A B Rule of Conduction Complements – Pull-up network is complement of pull-down – Parallel - series, series - parallel Circuits and Layout CMOS VLSI Design Slide 7

Compound Gates Compound gates can do any inverting function Ex: Y (A.B C.D)’ A C A C B D B D (a) A (b) B C D (c) C D A B (d) C D A B A B C D Y A C B D Y (f) (e) Circuits and Layout CMOS VLSI Design Slide 8

Example: O3AI Y ((A B C).D)’ Circuits and Layout CMOS VLSI Design Slide 9

Example: O3AI Y ((A B C).D)’ A B C D Y D A Circuits and Layout B C CMOS VLSI Design Slide 10

Signal Strength Strength of signal – How close it approximates ideal voltage source VDD and GND rails are strongest 1 and 0 nMOS pass strong 0 – But degraded or weak 1 pMOS pass strong 1 – But degraded or weak 0 Thus nMOS are best for pull-down network Circuits and Layout CMOS VLSI Design Slide 11

Pass Transistors Transistors can be used as switches g s d g s d Circuits and Layout CMOS VLSI Design Slide 12

Pass Transistors Transistors can be used as switches g 0 g s d s d g 1 s d g 0 g s d s 1 Input d g 1 s Circuits and Layout Input g 1 Output 0 strong 0 d CMOS VLSI Design 0 g 1 g 0 g 0 degraded 1 Output degraded 0 strong 1 Slide 13

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Circuits and Layout CMOS VLSI Design Slide 14

Transmission Gates Pass transistors produce degraded outputs Transmission gates pass both 0 and 1 well Input g a b gb a g 0, gb 1 a b g 1, gb 0 0 strong 0 g 1, gb 0 a b g 1, gb 0 strong 1 1 g g b gb Circuits and Layout a g b gb Output a b gb CMOS VLSI Design Slide 15

Tristates Tristate buffer produces Z when not enabled EN A 0 0 0 1 1 0 1 1 EN Y Y A EN Y A EN Circuits and Layout CMOS VLSI Design Slide 16

Tristates Tristate buffer produces Z when not enabled EN A Y 0 0 Z 0 1 Z 1 0 0 1 1 1 EN Y A EN Y A EN Circuits and Layout CMOS VLSI Design Slide 17

Nonrestoring Tristate Transmission gate acts as tristate buffer – Only two transistors – But nonrestoring Noise on A is passed on to Y EN A Y EN Circuits and Layout CMOS VLSI Design Slide 18

Tristate Inverter Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A EN Y EN Circuits and Layout CMOS VLSI Design Slide 19

Tristate Inverter Tristate inverter produces restored output – Violates conduction complement rule – Because we want a Z output A A A EN Y Y Y EN 0 Y 'Z' EN 1 Y A EN Circuits and Layout CMOS VLSI Design Slide 20

Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 0 X 0 0 X 1 1 0 X 1 1 X Circuits and Layout S Y CMOS VLSI Design D0 0 D1 1 Y Slide 21

Multiplexers 2:1 multiplexer chooses between two inputs S D1 D0 Y 0 X 0 0 0 X 1 1 1 0 X 0 1 1 X 1 Circuits and Layout CMOS VLSI Design S D0 0 D1 1 Y Slide 22

Gate-Level Mux Design Y SD1 SD0 (too many transistors) How many transistors are needed? Circuits and Layout CMOS VLSI Design Slide 23

Gate-Level Mux Design Y SD1 SD0 (too many transistors) How many transistors are needed? 20 D1 S D0 D1 S D0 Circuits and Layout Y 4 2 4 2 4 2 Y 2 CMOS VLSI Design Slide 24

Transmission Gate Mux Nonrestoring mux uses two transmission gates Circuits and Layout CMOS VLSI Design Slide 25

Transmission Gate Mux Nonrestoring mux uses two transmission gates – Only 4 transistors S D0 Y S D1 S Circuits and Layout CMOS VLSI Design Slide 26

Inverting Mux Inverting multiplexer – Use compound AOI22 – Or pair of tristate inverters – Essentially the same thing Noninverting multiplexer adds an inverter D0 S S D1 D0 D1 S S Y S Circuits and Layout S S Y S S CMOS VLSI Design D0 0 D1 1 Y Slide 27

4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects Circuits and Layout CMOS VLSI Design Slide 28

4:1 Multiplexer 4:1 mux chooses one of 4 inputs using two selects – Two levels of 2:1 muxes – Or four tristates S1S0 S1S0 S1S0 S1S0 D0 S0 D0 0 D1 1 D2 0 D3 1 S1 D1 0 1 Y Y D2 D3 Circuits and Layout CMOS VLSI Design Slide 29

D Latch When CLK 1, latch is transparent – D flows through to Q like a buffer When CLK 0, the latch is opaque – Q holds its old value independent of D a.k.a. transparent latch or level-sensitive latch D Latch CLK Circuits and Layout CLK D Q Q CMOS VLSI Design Slide 30

D Latch Design Multiplexer chooses D or old Q CLK D 1 CLK Q Q Q D Q 0 CLK CLK CLK Circuits and Layout CMOS VLSI Design Slide 31

D Latch Operation Q D CLK 1 Q Q D Q CLK 0 CLK D Q Circuits and Layout CMOS VLSI Design Slide 32

D Flip-flop When CLK rises, D is copied to Q At all other times, Q holds its value a.k.a. positive edge-triggered flip-flop, master-slave flip-flop CLK CLK D Flop D Q Circuits and Layout Q CMOS VLSI Design Slide 33

D Flip-flop Design Built from master and slave D latches CLK CLK CLK CLK QM Latch Latch CLK D QM D Circuits and Layout CLK Q CLK CLK Q CLK CMOS VLSI Design CLK Slide 34

D Flip-flop Operation D QM Q CLK 0 D QM Q CLK 1 CLK D Q Circuits and Layout CMOS VLSI Design Slide 35

Race Condition Back-to-back flops can malfunction from clock skew – Second flip-flop fires late – Sees first flip-flop change and captures its result – Called hold-time failure or race condition CLK1 CLK2 Q1 Circuits and Layout Flop D Flop CLK1 CLK2 Q2 Q1 Q2 CMOS VLSI Design Slide 36

Nonoverlapping Clocks Nonoverlapping clocks can prevent races – As long as nonoverlap exceeds clock skew We will use them in this class for safe design – Industry manages skew more carefully instead 2 1 QM D 2 2 2 Q 1 1 1 1 2 Circuits and Layout CMOS VLSI Design Slide 37

Gate Layout Layout can be very time consuming – Design gates to fit together nicely – Build a library of standard cells Standard cell design methodology – VDD and GND should abut (standard height) – Adjacent gates should satisfy design rules – nMOS at bottom and pMOS at top – All gates include well and substrate contacts Circuits and Layout CMOS VLSI Design Slide 38

Example: Inverter Circuits and Layout CMOS VLSI Design Slide 39

Example: NAND3 Horizontal N-diffusion and p-diffusion strips Vertical polysilicon gates Metal1 VDD rail at top Metal1 GND rail at bottom 32 by 40 Circuits and Layout CMOS VLSI Design Slide 40

Stick Diagrams Stick diagrams help plan layout quickly – Need not be to scale – Draw with color pencils or dry-erase markers Circuits and Layout CMOS VLSI Design Slide 41

Wiring Tracks A wiring track is the space required for a wire – 4 width, 4 spacing from neighbor 8 pitch Transistors also consume one wiring track Circuits and Layout CMOS VLSI Design Slide 42

Well spacing Wells must surround transistors by 6 – Implies 12 between opposite transistor flavors – Leaves room for one wire track Circuits and Layout CMOS VLSI Design Slide 43

Area Estimation Estimate area by counting wiring tracks – Multiply by 8 to express in Circuits and Layout CMOS VLSI Design Slide 44

Example: O3AI Sketch a stick diagram for O3AI and estimate area – Y ((A B C).D)’ Circuits and Layout CMOS VLSI Design Slide 45

Example: O3AI Sketch a stick diagram for O3AI and estimate area – Y ((A B C).D)’ Circuits and Layout CMOS VLSI Design Slide 46

Example: O3AI Sketch a stick diagram for O3AI and estimate area – Y ((A B C).D)’ Circuits and Layout CMOS VLSI Design Slide 47