Chapter 7: Microprogrammed Control Dr. Lo’ai Tawalbeh cpe

Chapter 7: Microprogrammed Control Dr. Lo’ai Tawalbeh cpe 252: Computer Organization 1

Control Unit Implementation Hardwired Memory Instruction code Combinational Logic Circuits Sequence Counter . . Control signals Microprogrammed Memory CAR: Control Address Register CDR: Control Data Register Instruction code Next Address Generator (sequencer) CAR Control Memory cpe 252: Computer Organization CDR Decoding Circuit . . Control signals 2

Microprogrammed Control Unit Control signals – Group of bits used to select paths in multiplexers, decoders, arithmetic logic units Control variables – Binary variables specify microoperations Certain microoperations initiated while others idle Control word – String of 1’s and 0’s represent control variables cpe 252: Computer Organization 3

Microprogrammed Control Unit Control memory – Memory contains control words Microinstructions – Control words stored in control memory – Specify control signals for execution of microoperations Microprogram – Sequence of microinstructions cpe 252: Computer Organization 4

Control Memory Read-only memory (ROM) Content of word in ROM at given address specifies microinstruction Each computer instruction initiates series of microinstructions (microprogram) in control memory These microinstructions generate microoperations to – – – – Fetch instruction from main memory Evaluate effective address Execute operation specified by instruction Return control to fetch phase for next instruction Address Control memory (ROM) cpe 252: Computer Organization Control word (microinstruction) 5

Microprogrammed Control Organization External input Next Address Generator (sequencer) CAR Control Memory (ROM) CDR Control word Control memory – Contains microprograms (set of microinstructions) – Microinstruction contains Bits initiate microoperations Bits determine address of next microinstruction Control address register (CAR) – Specifies address of next microinstruction cpe 252: Computer Organization 6

Microprogrammed Control Organization Next address generator (microprogram sequencer) – Determines address sequence for control memory Microprogram sequencer functions – Increment CAR by one – Transfer external address into CAR – Load initial address into CAR to start control operations cpe 252: Computer Organization 7

Microprogrammed Control Organization Control data register (CDR)- or pipeline register – Holds microinstruction read from control memory – Allows execution of microoperations specified by control word simultaneously with generation of next microinstruction Control unit can operate without CDR External input Next Address Generator (sequencer) CAR Control Memory (ROM) cpe 252: Computer Organization Control word 8

Microprogram Routines Routine – Group of microinstructions stored in control memory Each computer instruction has its own microprogram routine to generate microoperations that execute the instruction cpe 252: Computer Organization 9

Microprogram Routines Subroutine – Sequence of microinstructions used by other routines to accomplish particular task Example – Subroutine to generate effective address of operand for memory reference instruction Subroutine register (SBR) – Stores return address during subroutine call cpe 252: Computer Organization 10

Conditional Branching Branching from one routine to another depends on status bit conditions Status bits provide parameter info such as – Carry-out of adder – Sign bit of number – Mode bits of instruction Info in status bits can be tested and actions initiated based on their conditions: 1 or 0 Unconditional branch – Fix value of status bit to 1 cpe 252: Computer Organization 11

Mapping of Instruction Each computer instruction has its own microprogram routine stored in a given location of the control memory Mapping – Transformation from instruction code bits to address in control memory where routine is located cpe 252: Computer Organization 12

Mapping of Instruction Example – Mapping 4-bit operation code to 7-bit address OP-codes of Instructions ADD 0000 0001 AND 0010 LDA Mapping bits 0 xxxx 00 Control memory Address 0 0000 00 ADD Routine 0 0001 00 AND Routine 0 0010 00 LDA Routine cpe 252: Computer Organization 13

Address Sequencing Address sequencing capabilities required in control unit – Incrementing CAR – Unconditional or conditional branch, depending on status bit conditions – Mapping from bits of instruction to address for control memory – Facility for subroutine call and return cpe 252: Computer Organization 14

Address Sequencing Instruction code Mapping logic Status bits Branch MUX logic select Multiplexers Subroutine Register (SBR) Control Address Register (CAR) Incrementer Control memory (ROM) select a status bit Branch address Microoperations cpe 252: Computer Organization 15

Microprogram Example MUX Computer Configuration 10 0 AR Address 10 0 Memory 2048 x 16 PC MUX 6 0 SBR 6 0 15 CAR Control memory 128 x 20 Control unit cpe 252: Computer Organization DR 0 Arithmetic logic and shift unit 15 0 AC 16

Microprogram Example Computer instruction format 15 14 11 10 Opcode I 0 Address Four computer instructions Symbol OP-code ADD 0000 BRANCH 0001 STORE 0010 EXCHANGE AC Description AC AC M[EA] if (AC 0) then (PC EA) M[EA] AC 0011 AC M[EA], M[EA] EA is the effective address Microinstruction Format 3 F1 3 F2 3 F3 2 CD 2 BR 7 AD F1, F2, F3: Microoperation fields CD: Condition for branching BR: Branch field AD: Address field cpe 252: Computer Organization 17

Microinstruction Fields F1 000 001 010 011 100 101 110 111 Microoperation None AC AC DR AC 0 AC AC 1 AC DR AR DR(0-10) AR PC M[AR] DR Symbol NOP ADD CLRAC INCAC DRTAC DRTAR PCTAR WRITE F3 000 001 010 011 100 101 110 111 F2 000 001 010 011 100 101 110 111 Microoperation None AC AC DR AC AC’ AC shl AC AC shr AC PC PC 1 PC AR Reserved Microoperation None AC AC - DR AC AC DR AC AC DR DR M[AR] DR AC DR DR 1 DR(0-10) PC Symbol NOP SUB OR AND READ ACTDR INCDR PCTDR Symbol NOP XOR COM SHL SHR INCPC ARTPC cpe 252: Computer Organization 18

Microinstruction Fields CD 00 01 10 11 BR 00 Condition Always 1 DR(15) AC(15) AC 0 Symbol JMP 01 CALL 10 11 RET MAP Symbol U I S Z Comments Unconditional branch Indirect address bit Sign bit of AC Zero value in AC Function CAR AD if condition 1 CAR CAR 1 if condition 0 CAR AD, SBR CAR 1 if condition 1 CAR CAR 1 if condition 0 CAR SBR (Return from subroutine) CAR(2-5) DR(11-14), CAR(0,1,6) 0 cpe 252: Computer Organization 19

Symbolic Microinstruction Sample Format Label Label: Micro-ops CD BR AD may be empty or may specify symbolic address terminated with colon Micro-ops consists of 1, 2, or 3 symbols separated by commas CD one of {U, I, S, Z} U: Unconditional Branch I: Indirect address bit S: Sign of AC Z: Zero value in AC BR one of {JMP, CALL, RET, MAP} AD one of {Symbolic address, NEXT, empty} cpe 252: Computer Organization 20

Fetch Routine Fetch routine - Read instruction from memory - Decode instruction and update PC Microinstructions for fetch routine: AR PC DR M[AR], PC PC 1 AR DR(0-10), CAR(2-5) DR(11-14), CAR(0,1,6) 0 Symbolic microprogram for fetch routine: FETCH: ORG 64 PCTAR READ, INCPC DRTAR U JMP NEXT U JMP NEXT U MAP Binary microporgram for fetch routine: Binary address 1000000 1000001 1000010 F1 110 000 101 F2 000 100 000 F3 000 101 000 CD 00 00 00 cpe 252: Computer Organization BR 00 00 11 AD 1000001 1000010 0000000 21

Symbolic Microprogram Control memory: 128 20-bit words First 64 words: Routines for 16 machine instructions Last 64 words: Used for other purpose (e.g., fetch routine and other subroutines) Mapping: OP-code XXXX into 0XXXX00, first address for 16 routines are 0(0 0000 00), 4(0 0001 00), 8, 12, 16, 20, ., 60 Partial Symbolic Microprogram Label ADD: BRANCH: OVER: STORE: EXCHANGE: FETCH: INDRCT: Microops BR AD I U U CALL JMP JMP INDRCT NEXT FETCH ORG 4 NOP NOP NOP ARTPC S U I U JMP JMP CALL JMP OVER FETCH INDRCT FETCH ORG 8 NOP ACTDR WRITE I U U CALL JMP JMP INDRCT NEXT FETCH ORG 12 NOP READ ACTDR, DRTAC WRITE I U U U CALL JMP JMP JMP INDRCT NEXT NEXT FETCH ORG 0 NOP READ ADD ORG 64 PCTAR READ, INCPC DRTAR READ DRTAR cpe CD 252: U JMP NEXT U JMP NEXT U MAP U JMP NEXT Computer Organization U RET 22

Binary Microprogram Micro Routine AD ADD Address Decimal Binary 0 1 0000000 000 0000001 000 2 0000010 F1 Binary Microinstruction F2 F3 CD BR 000 100 001 000 000 000 00 000 00 00 1000011 0000010 00 000 000 000 00 00 000 000 000 000 000 101 111 000 000 000 110 000 000 000 000 01 01 1000000 3 1000000 BRANCH STORE 0000011 4 0000100 000 5 0000101 000 6 0000110 000 7 0000111 000 8 0001000 000 9 0001001 000 10 0001010 10 00 000 00 00 0000110 1000000 1000011 1000000 1000011 0001010 00 000 000 00 00 000 001 000 000 01 000 00 00 00 01 00 00 00 01 00 01 01 1000000 11 1000000 EXCHANGE 12 0001011 0001100 000 13 0001101 01 1000011 0001110 14 0001110 100 101 000 00 00 15 0001111 111 000 000 00 00 0001111 1000000 cpe 252: Computer Organization 23

Design of Control Unit microoperation fields F1 F2 F3 3 x 8 decoder 3 x 8 decoder 3 x 8 decoder 7 6 54 3 21 0 7 6 54 3 21 0 7 6 54 3 21 0 AND ADD Arithmetic logic and shift unit DRTAR PCTAR DRTAC From From PC DR(0-10) Select Load Load AC DR AC 0 1 Multiplexers AR cpe 252: Computer Organization Clock 24

Microprogram Sequencer External (MAP) L I0 Input I1 logic T 1 I S Z 3 2 1 0 S1 MUX1 S0 SBR Load Incrementer MUX2 Test Select Clock CAR Control memory Microops . CD BR AD . cpe 252: Computer Organization 25

Input Logic for Microprogram Sequencer 1 From I CPU S MUX2 Z L Test BR field of CS Select T Input I0 logic I1 L(load SBR with PC) for subroutine Call S0 for next address S1 selection CD Field of CS Input Logic I1I0T Meaning Source of Address S1S0 000 001 010 011 10x 11x In-Line JMP In-Line CALL RET MAP 00 01 00 01 10 11 CAR 1 CS(AD) CAR 1 CS(AD) and SBR - CAR 1 SBR DR(11-14) S1 I1 S0 I0I1 I1’T L I1’I0T cpe 252: Computer Organization L 0 0 0 1 0 0 26